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1.The following questions investigate the impact of small and simple caches using CACTI, and assume a 90 nm (0.09 µm) technology.
a. Compare the access times of 32 KB caches with 64-byte blocks and a single bank. What is the relative access times of two-way and four-way set associative caches in comparison to a direct-mapped organization?
b. Compare the access times of two-way set-associative caches with 64-byte blocks and a single bank. What is the relative access times of 32 KB
and 64 KB caches in comparison to a 16 KB cache?
c. Does the access time for a typical level 1 cache organization increase with size roughly as the capacity in bytes B, the square root of B, or the log of B ?
d. Find the cache organization with the lowest average memory access time given the miss ratio table in Figure 5.29 and a cache access time budget of 0.90 ns. What is this organization, and does it have the lowest miss rate of all organizations for its capacity?
2.Design a two-way set associative single-word block cache. The cache can store a total of 256 words. Draw the implementation diagram showing the 32-bit address, the tag and index, the Hit signal, and the data bus. Indicate the corresponding bit allocations for the tag and index.
3.A RAM chip 4096 x 8 bits has two enable lines. How many pains are needed for the integrated circuit package of Draw a block diagram and label all input and outputs pins of the RAM. What is the main feature of random access memory?
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4. What is Memory Hierarchy Technology? Explain why cost increases and size decrease of memory in bytes when we go lower level to higher level of memory hierarchy.
5.A two level memory hierarchy m1 and m2 has size s1=256 KB and s2=2 MB. The hit ratio at m1 is 0.67 and m2 at 1. The cost per byte at m1 is Rs. 4.0 and at m2 is Rs. 0.5 per byte. Let, r = Teff/T1 where, T1= 0.5, T2 = 1 i. Find the value of r. ii. Find Avg. cost of above memory system.
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