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1.A main memory unit with a capacity of 4 megabytes is built using 1M*1 bit DRAM chips .Each DRAM chip has 1k rows of cells with 1k cells in each row .If the time taken for 1 single refresh operation is 100 nanoseconds, then calculate the time required to perform one refresh operation on all the cells in the memory unit?
2.Indicate which predefined c ++types would most appropriately model each of the following(please explain why)
a.) a chessboard
b.) information about a single product in an inventory-control program
c.) a list of famous quotations
d.) the casualty figures for highway accidents in Texas from 1995-2005
e.) the casualty figures forhighway accidents in each of the states from 1995-2005
f.) the casualty figures for highway accidents in each of the states subdivided by month
g.)an electronic address book (name, address, and number)
h.)a collection of hourly temperatures for a 24 hour period
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3.Assume the system is your desktop PC and only one core on the CMP is active. Assume there is only one memory channel.
a. How many DRAMs are on the DIMM if 512 Mbit DRAMs are used, and how many data I/Os must each DRAM have if only one DRAM connects to each DIMM data pin?
b. What burst length is required to support 32-byte versus 64-byte level 2 cache blocks?
c. What is the peak bandwidth ratio between the DIMMs for reads from an active page?
d. How much time is required from the presentation of the activate command until the last requested bit of data from the DRAM transitions from valid to invalid for the DDR2-533 1 GB CL = 4 DIMM?
e. What is the relative latency when using the DDR2-533 DIMM of a read requiring a bank activate versus one to an already open page, including the time required to process the miss inside the processor?
4.The 2125A is a static-RAM IC that has a capacity of 1K × 1, one active-LOW chip select input, and separate data input and output. Show how to combine several 2125A ICs to form a 1K × 8 module.
5.We want to combine several 2K × 8 PROMs to produce a total capacity of 8K × 8. How many PROM chips are needed? How many address bus lines are required?
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