Online Computer Architecture and Memory Organization Homework help
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1.Consider a cache (M1) and memory (M2) hierarchy with the following characteristics: M1 : 16 K words, 50 ns access time M2 : 1 M words, 400 ns access time Assume 8 words cache blocks and a set size of 256 words with set associative mapping. Show the mapping between M2 and M1 and calculate the Effective Memory Access time with a cache hit ratio of h = .95.
2.Describe the internal architecture of a ROM that stores 4K bytes and uses a square register array.
3.The 2147H is an NMOS RAM that is organized as a 4K × 1 with separate data input and output and a single active-LOW chip select input. Draw the logic symbol for this chip, showing all pin functions.
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4.For each item below, indicate the type of memory being described: MROM, PROM, EPROM, EEPROM, flash. Some items will correspond to more than one memory type.
(a) Can be programmed by the user but cannot be erased.
(b) Is programmed by the manufacturer.
(c) Is volatile.
(d) Can be erased and reprogrammed over and over.
(e) Individual words can be erased and rewritten.
(f) Is erased with UV light.
(g) Is erased electrically.
(h) Uses fusible links.
(i) Can be erased in bulk or in sectors of 512 bytes.
(j) Does not have to be removed from the system to be erased and reprogrammed.
(k) Requires a special supply voltage for reprogramming.
(l) Erase time is about 15 to 20 min.
5.A computer employs RAM chips of 256*8 and ROM chips of 1024*8.the computer system needs 2k bytes of ram ,4k bytes of ROM and four interface units ,each with four registers .A memory mapped i/o configuration is used the two highest order bits of address bus are assigned 00 for RAM,01 FOR ROM,AND 10 FOR INTERFACE REGISTERS, how many RAM and ROM chips are needed?
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